View CDC3207G-C_306382.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

DATA SHEET
MICRONAS
CDC 3207G-C3 Automotive Controller
Edition Feb. 10, 2005 6251-589-1DS
MICRONAS
CDC 3207G-C3
Contents Page 3 3 6 7 9 9 10 10 11 13 13 14 15 17 19 21 23 23 25 25 27 28 Section 1. 1.1. 1.2. 1.3. 2. 2.1. 2.2. 2.3. 2.4. 3. 3.1. 3.2. 3.3. 3.4. 4. 5. 6. 6.1. 7. 7.1. 8. 9. Title Introduction Features Abbreviations Block Diagram Packages and Pins Package Outline Dimensions Pin Assignment Pin Function Description External Components Electrical Data Absolute Maximum Ratings Recommended Operating Conditions Characteristics Recommended Quartz Crystal Characteristics CPU and Clock System Memory and Special Function ROM (SFR) System Core Logic Control Word (CW) Hardware Options Functional Description Differences Data Sheet History
DATA SHEET
2
Feb. 10, 2005; 6251-589-1DS
Micronas
DATA SHEET
CDC 3207G-C3
1. Introduction
Release Note: Revision bars changes to the previous edition. indicate significant CAN interfaces, PWM outputs and a crystal clock multiplying PLL. This document provides MCM Flash hardware-specific information. General information on operating the IC can be found in the document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1DS)".
The device is a microcontroller for use in automotive applications. The on-chip CPU is an ARM processor ARM7TDMI with 32-bit data and address bus, which supports Thumb format instructions. The chip contains timer/counters, an interrupt controller, a multichannel A/D converter, a stepper motor and LCD driver,
1.1. Features
Table 1-1: CDC32xxG-C Family Feature List This Device: Item CDC3205GC EMU CDC3207GC MCM Flash CDC3217GC MCM Flash CDC3257GC2 MCM Flash CDC3272GC Mask ROM CDC3231GC Mask ROM
Core CPU CPU-active operation modes Power-saving operation modes (CPU inactive) CPU clock multiplication EMI reduction mode Oscillators RAM, zero wait state, 32 bit wide ROM 32-bit ARM7TDMI DEEP SLOW, SLOW, FAST and PLL IDLE, WAKE and STANDBY PLL delivering up to 50 MHz selectable in PLL mode 4 to 5 MHz quartz and 32 kHz internal RC 32 Kbyte ROMless, ext. up to 4 M x 32/ 8 M x 16 512-Kbyte Flash (256 K x 16) top-boot conf. 1024-Kbyte Flash (512 K x 16) top-boot conf. 12 Kbyte 256-Kbyte Flash (128 K x 16) top-boot conf. 16 Kbyte 384 Kbyte (96 K x 32/ 192 K x 16) 6 Kbyte 128 Kbyte (32 K x 32/ 64 K x 16)
Boot ROM Digital watchdog Central clock divider Interrupt controller expanding IRQ Port interrupts including slope selection Port wake-up inputs including slope/level selection
8 Kbyte (special function ROM) 40 inputs, 16 priority levels 26 inputs, 16 priority levels 5 inputs
6 inputs 10 inputs
Micronas
Feb. 10, 2005; 6251-589-1DS
3
CDC 3207G-C3
Table 1-1: CDC32xxG-C Family Feature List This Device: Item CDC3205GC EMU CDC3207GC MCM Flash CDC3217GC MCM Flash CDC3257GC2 MCM Flash CDC3272GC Mask ROM
DATA SHEET
CDC3231GC Mask ROM
Patch module Boot system Device lock module Analog Reset/Alarm Clock and supply supervision 10-bit ADC, charge balance type ADC reference Comparators LCD Communication DMA UART Synchronous serial peripheral interfaces Full CAN modules V2.0B each with a 32-object RAM (LCAN000E) DIGITbus I2C Graphics bus interface Input & Output Universal ports selectable as 4:1-mux LCD segment/backplane lines or digital I/O ports
10 ROM locations allows in-system downloading of external code to Flash memory via JTAG inhibits access to internal firmware, lock can be set by customer -
combined input for regulator input supervision 16 channels (each selectable as digital input) VREF pin, P1.0 pin, P1.1 pin or VREFINT internal bandgap selectable P06COMP with 1/2 AVDD reference, WAITCOMP with internal bandgap reference internal processing of all analog voltages for the LCD driver
3 DMA channels, one each for serving the graphics bus interface, SPI0 and SPI1 2: UART0 and UART1 2: SPI0 and SPI1, DMA supported 4: CAN0, CAN1, CAN2 and CAN3 2: CAN0 and CAN1
UART0
1: CAN0
1 master module 2 master modules: I2C0 and I2C1 8-bit data bus, DMA supported, e.g., for connection of EPSON SED 1560 LCD controller
I2C0 -
up to 52 I/O or 48 LCD segment lines (= 192 segments), individually configurable as I/O or LCD
up to 50 I/O or 46 LCD segment lines (= 184 segments)
Universal port slew rate Stepper motor control modules with high-current ports
SW-selectable 7 modules, 32 dI/dt-controlled ports 4 modules 23 dI/dtcontrolled ports
4
Feb. 10, 2005; 6251-589-1DS
Micronas
DATA SHEET
CDC 3207G-C3
Table 1-1: CDC32xxG-C Family Feature List This Device: Item CDC3205GC EMU CDC3207GC MCM Flash CDC3217GC MCM Flash CDC3257GC2 MCM Flash CDC3272GC Mask ROM CDC3231GC Mask ROM 5 modules: PWM0/1, PWM2/3, PWM4/5, PWM6/7, PWM8/9 -
PWM modules, each configurable as two 8-bit PWMs or one 16-bit PWM
6 modules: PWM0/1, PWM2/3, PWM4/5, PWM6/7, PWM8/9 and PWM10/ 11
Pulse/frequency modulator Audio module with auto-decay SW-selectable clock outputs Polling/flash timer output Timers & Counters 16-bit free-running counters with capture/compare modules 16-bit timers 8-bit timers Real-time clock, delivering hours, minutes and seconds Miscellaneous Scalable layout in CAN, RAM and ROM Various HW options selectable at random JTAG interface On-chip debug aids
2: PFM0 and PFM1 2 1 high-current port output operable in power-saving operation modes
CCC0 with 4 CAPCOM CCC1 with 2 CAPCOM 1: T0 4: T1, T2, T3 and T4
CCC0 with 4 CAPCOM
-
set by copy from user program storage during system start-up allows Flash programming Embedded trace module, JTAG JTAG
Core bond-out Supply voltage Case temperature range Package Type Bonded pins
-
3.5 to 5.5 V (limited I/O performance below 4.5 V) 0 C to +70 C -40 C to +105 C
ceramic 257PGA 256
plastic 128QFP 0.5 mm pitch 128 128 128 126 111
ARM and Thumb are the registered trademarks of ARM Limited. ARM7TDMI is the trademark of ARM Limited.
Micronas
Feb. 10, 2005; 6251-589-1DS
5
CDC 3207G-C3
1.2. Abbreviations
ADC AM CAN CAPCOM CCC CPU DMA ERM ETM I2C LCD P06COMP PWM SM SPI T UART WAITCOMP Analog-to-Digital Converter Audio Module Controller Area Network Capture/Compare Capture/Compare Counter Central Processing Unit Direct Memory Access EMI Reduction Mode Embedded Trace Module I2C Bus Interface Liquid Crystal Display P0.6 Alarm Comparator Pulse Width Modulator Stepper Motor Control Module Serial Synchronous Peripheral Interface Timer Universal Asynchronous Receiver/Transmitter Wait Comparator
DATA SHEET
6
Feb. 10, 2005; 6251-589-1DS
Micronas
DATA SHEET
CDC 3207G-C3
1.3. Block Diagram
FVDD FVSS 3.3 V Reg.
UVDD UVSS 2.5 V Reg.
VDD VSS Reset/Alarm Test Watchdog Clock PLL/ERM RESETQ TEST TEST2 XTAL1 XTAL2
WAIT WAITH VREFINT VREF AVDD AVSS BVDD 8 PPort0 ARM7TDMI CPU 2.5 V Reg.
RC Oscillator 40-Input Interrupt Controller RTC Power Saving JTAG Test and Debug Interface
SRAM 8K x 32 DMA Logic Bridge 32 Wait Comp. P06 Comp. Memory Controller 16
5
PPort1
8
UPort0
Flash 256K x 16 Special Function ROM 4K x 16 Patch 10 Locations
8
2
PPort2
UPort1
8
HPort0
4
Bandgap Ref. 10-bit ADC Bridge 8
4
HPort1
Device Lock Module
UPort2
7
HPort2
UPort3
4
UART 0 UART 1
LCD Control Audio Module
Stepper Motor Control
8-bit PWM 0 8/16-bit PWM 1
16-bit Timer 0 8-bit Timer 1 8-bit Timer 2 8-bit Timer 3 8-bit Timer 4
16-bit CCC 0 CAPCOM 0 CAPCOM 1 CAPCOM 2
8
HPort3
4
SPI 0 SPI 1 CAN 0 CAN 1 CAN 2 CAN 3 DIGITbus Clock Out 0
UPort4
4
HPort4
8-bit PWM 2
CAPCOM 3 16-bit CCC 1 CAPCOM 4 UPort6 CAPCOM 5 3 UPort5 4
4
Clock Out 1 Pulse/Freq. Modulator 0 Pulse/Freq. Modulator 1
8/16-bit PWM 3 8-bit PWM 4 8/16-bit PWM 5 8-bit PWM 6 8/16-bit PWM 7 8-bit PWM 8 8/16-bit PWM 9 8-bit PWM 10
4
4
HPort7
HPort6
HPort5
4
I2 C
UPort7
0
4
HVDD0 HVSS0 HVDD1 HVSS1 HVDD2 HVSS2 HVDD3 HVSS3
I2 C 1 Graphics Bus
UPort8
8/16-bit PWM 11
6
Fig. 1-1: CDC3207G-C block diagram
Micronas
Feb. 10, 2005; 6251-589-1DS
7
CDC 3207G-C3
DATA SHEET
8
Feb. 10, 2005; 6251-589-1DS
Micronas
DATA SHEET
CDC 3207G-C3
2. Packages and Pins
2.1. Package Outline Dimensions
Fig. 2-1: PMQFP128-2: Plastic Metric Quad Flat Package, 128 leads, 14 x 20 x 2.7 mm3 Ordering code: MF Weight approximately 1.8 g
Micronas
Feb. 10, 2005; 6251-589-1DS
9
CDC 3207G-C3
2.2. Pin Assignment
Pin Functions LCD Port Port Basic Mode Special Out Special In Function SEG3.1 CC1-OUT CC1-IN / TMS U3.1 SEG3.0 CC2-OUT CC2-IN / TDI U3.0 TEST2 UVDD UVSS SEG2.6 DIGIT-OUT DIGIT-IN U2.6 SEG2.5 CC1-OUT UART0-RX U2.5 SEG2.4 UART0-TX DIGIT-IN/CC1-IN U2.4 SEG2.3 CC2-OUT UART1-RX U2.3 SEG2.2 UART1-TX CC2-IN U2.2 SEG7.7 CO0 U7.7/GD7 SEG7.6 CO1 U7.6/GD6 SEG7.5 LCK/PFM1 U7.5/GD5 SEG7.4 CC5-OUT CC5-IN U7.4/GD4 FVDD FVSS SEG5.3 CC4-OUT CC4-IN U5.3/GD3 SEG5.2 SDA1 SDA1 U5.2/GD2 SEG5.1 SCL1 SCL1 U5.1/GD1 SEG5.0 PFM0 U5.0/GD0 SEG2.1 SDA0 WP6/SDA0/CAN0U2.1 RX SEG2.0 SCL0/CAN0-TX SCL0 U2.0 SEG1.7 PFM0 WP0/PINT0 U1.7 SEG1.6 INTRES/CO0 PINT1 U1.6 SEG1.5 CO1/CO0Q PINT2 U1.5 TEST RESETQ/ALARMQ XTAL2 XTAL1 VSS VDD SEG1.4 ITSTOUT/AM-OUT U1.4 SEG1.3 MTO/AM-PWM WP3 U1.3 SEG1.2 INTRES/T0-OUT MTI/ITSTIN U1.2 SEG1.1 T1-OUT U1.1 SEG1.0 T2-OUT U1.0 SEG0.7 T3-OUT WP4 U0.7 SEG0.6 CC3-OUT/T4-OUT CC3-IN U0.6 SEG0.5 CC3-OUT PINT4 U0.5 SEG0.4 CO1 PINT5 U0.4 SEG0.3 PWM0 U0.3 SEG0.2 PWM1 U0.2 SEG0.1 PWM2 U0.1 SEG0.0 PWM3 U0.0 SME1+/PWM4 SME-COMP3 H7.3 SME1-/PWM6 SME-COMP2 H7.2 SME2+/PWM8 SME-COMP1 H7.1 SME2-/PWM9 SME-COMP0 H7.0 HVDD2 HVSS2 PWM8 H6.3 PWM9 H6.2 PWM10 H6.1 PWM11 H6.0 SMD1+ SMD-COMP3 H5.3 SMD1SMD-COMP2 H5.2 HVDD0 HVSS0 SMD2+ SMD-COMP1 H5.1 SMD2SMD-COMP0 H5.0 SMA1+ SMA-COMP3 H4.3 SMA1SMA-COMP2 H4.2 SMA2+ SMA-COMP1 H4.1 SMA2SMA-COMP0 H4.0 Not Pin e No. 116 117 118 119 120 121 122 123 124 125 126 127 128 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 Pin Not No. e Basic Function 115 U3.2 114 U3.3 113 U3.4 112 U3.5 111 U3.6 110 U3.7 109 U4.0 108 U4.1 107 U4.2 106 U4.3 105 1,2 U8.0 104 1,2 U8.1 103 1,2 U8.2 102 1,2 U8.3 101 1,2 U8.4 100 1,2 U8.5 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 1 1 1 1 U6.0 U6.1 U6.2 P2.0 P2.1 P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 WAITH WAIT BVDD AVSS AVDD VREFINT VREF P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 H0.0 H0.1 H0.2 H0.3 HVSS3 HVDD3 H1.0 H1.1 H1.2 H1.3 H2.0 H2.1 HVSS1 HVDD1 H2.2 H2.3 H3.0 H3.1 H3.2 H3.3
DATA SHEET
1,2 1,2 1,2 1,2 1,2 1,2 1 1 1 1
Pin Functions Port Port Special In Special Out CC0-IN / TCK CC0-OUT CO0/TDO SPI0-CLK-IN SPI0-CLK-OUT SPI0-D-IN TO3 SPI0-D-OUT SPI1-CLK-IN SPI1-CLK-OUT SPI1-D-IN CC0-OUT CC0-IN SPI1-D-OUT CAN0-TX CAN0-RX/WP5 TO2 CC4-OUT CC3-OUT LCD-CLK-IN CAN3-TX CAN3-RX/WP9 LCD-CLK-OUT LCD-SYNC-IN CAN2-TX CAN2-RX/PINT3/ LCD-SYNC-OUT WP8 CAN1-TX CAN1-RX/WP7 GOEQ GWEQ
LCD Mode SEG3.2 SEG3.3 SEG3.4 SEG3.5 SEG3.6 SEG3.7 BP0 BP1 BP2 BP3 SEG8.0 SEG8.1 SEG8.2 SEG8.3 SEG8.4 SEG8.5 SEG6.0 SEG6.1 SEG6.2
CC4-IN
128 1
116
115
103 102
P0.6 Comp.
38 39 51 52 64
65
1 1 1 1 1,2 1,2 1,2 1,2 1,2 1,2
1 1 1 1 1,2 1,2 1,2 1,2 1,2 1,2
VREF0/WP1 VREF1/WP2 PINT0 PINT1 PINT2 PINT3 PINT4 PINT5 SMG-COMP0 SMG-COMP1 SMG-COMP2 SMG-COMP3
SMG2-/PWM7 SMG2+/PWM5 SMG1-/PWM3/POL SMG1+/PWM1
SMF-COMP0 SMF-COMP1 SMF-COMP2 SMF-COMP3 SMC-COMP0 SMC-COMP1
SMF2SMF2+ SMF1SMF1+ SMC2SMC2+
NC = not connected, leave vacant (...) = future usage
SMC-COMP2 SMC-COMP3 SMB-COMP0 SMB-COMP1 SMB-COMP2 SMB-COMP3
SMC1SMC1+ SMB2SMB2+ SMB1SMB1+
Fig. 2-2: Pin assignment for PQFP128 package Note 1 denotes pins that will not be available in future 88-pin versions. Note 2 denotes pins that will not be available in future 104-pin versions.
2.3. Pin Function Description
(differing from document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1DS)) TEST2 For normal operation with internal code connect TEST2 to System Ground (no internal pull-down).
10
Feb. 10, 2005; 6251-589-1DS
Micronas
DATA SHEET
CDC 3207G-C3
2.4. External Components
FVDD
3.3 Tantal ESR < 14 470 n Ceramic X7R
3.3 V FVSS UVDD 5V Flash +5 V Supply
4 x 100 n to 150 n
+5 V Supply
100 n to 150 n
HVDD0 to 3 5V HVSS0 to 3 2.5 V
System Ground
UVSS VDD
10 Tantal Low ESR 220 n Ceramic X7R
System Ground
VSS
AVDD
100 n to 150 n
Analog Supply
XTAL1
18 p
5V 2.5 V
VREFINT
10 n, Ceramic
AVSS BVDD
150 n Ceramic, X7R
+5 V Supply 4.7 k
Analog Ground
18 p
XTAL2 RESETQ
47 n
Resetq System Ground
Fig. 2-3: CDC3207G-C: Recommended external supply and quartz connection. To provide effective decoupling and to improve EMC behavior, the small decoupling capacitors must be located as close to the supply pins as possible. The self-inductance of these capacitors and the parasitic inductance and capacitance of the interconnecting traces determine the self-resonant frequency of the decoupling network. Too low a frequency will reduce decoupling effectiveness, will increase RF emissions and may adversely affect device operation. XTAL1 and XTAL2 quartz connections are especially sensitive to capacitive coupling from other PC board signals. It is strongly recommended to place quartz and oscillation capacitors as close to the pins as possible and to shield the XTAL1 and XTAL2 traces from other signals by embedding them in a VSS trace. The RESETQ pin adjacent to XTAL2 should be supplied with a 47 nF capacitor, to prevent fast RESETQ transients from being coupled into XTAL2, to prevent XTAL2 from coupling into RESETQ, and to guarantee a time constant of 200 s sufficient for proper wake reset functionality.
Micronas
Feb. 10, 2005; 6251-589-1DS
11
CDC 3207G-C3
DATA SHEET
12
Feb. 10, 2005; 6251-589-1DS
Micronas
DATA SHEET
CDC 3207G-C3
3. Electrical Data
3.1. Absolute Maximum Ratings
Stresses beyond those listed in the "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only. Functional operation of the device at these conditions is not implied. Exposure to absolute maximum ratings conditions for extended periods will affect device reliability. This device contains circuitry to protect the inputs and outputs against damage due to high static voltages or electric fields; however, it is advised that normal precautions be taken to avoid application of any voltage higher than absolute maximum-rated voltages to this high-impedance circuit. Table 3-1: All voltages listed are referenced to ground (UVSS = HVSSn = AVSS = 0 V), except where noted. All ground pins except VSS must be connected to a low-resistive ground plane close to the IC. Symbol VSUP Parameter Main supply voltage Analog supply voltage SM supply voltage Flash supply voltage Core supply voltage PLL supply voltage ISUP Core supply current Main supply current Analog supply current SM supply current @TCASE = 105 C, duty factor = 0.71 1) Flash supply current PLL supply current Vin Input voltage Pin Name UVDD AVDD HVDD0 .. HVDD3 FVDD VDD BVDD VDD, VSS, UVDD, UVSS AVDD, AVSS HVDD0 .. HVDD3 HVSS0 .. HVSS3 FVDD, FVSS BVDD U ports, XTAL,RESETQ, TEST, TEST2 P ports VREF H ports Iin Io Input current Output current all inputs U ports, RESETQ, WAITH H ports toshsl Tj Ts Pmax
1)
Min. -0.3
Max. 6.0
Unit V
VREG
-0.3 -0.3 -100 -20 -250 -50 -20 UVSS - 0.5
4.0 3.0 100 20 250 50 20 UVDD + 0.7
V V mA mA mA mA mA V
UVSS - 0.5 HVSS - 0.5 0 -5 -60
AVDD + 0.7 HVDD + 0.7 2 5 60 indefinite
V V mA mA mA s C C W
Duration of short circuit to UVSS or UVDD, Port SLOW mode enabled Junction temperature under bias Storage temperature Maximum power dissipation
U ports, except in DP mode -45 -45
115 125 0.8
This condition represents the worst case load with regard to the intended application.
Micronas
Feb. 10, 2005; 6251-589-1DS
13
CDC 3207G-C3
3.2. Recommended Operating Conditions
DATA SHEET
Do not insert the device into a live socket. Instead, apply power by switching on the external power supply. Keep UVDD=AVDD during all power-up and power-down sequences. Failure to comply with the above recommendations will result in unpredictable behavior of the device and may result in device destruction. Functional operation of the device beyond those indicated in the "Recommended Operating Conditions" of this specification is not implied, may result in unpredictable behavior of the device and may reduce reliability and lifetime.
Table 3-2: All voltages listed are referenced to ground (UVSS = HVSSn = AVSS = 0 V), except where noted. All ground pins except VSS must be connected to a low-resistive ground plane close to the IC. Symbol VSUP HVSUP dVDD Parameter Main supply voltage Analog supply voltage SM supply voltage Ripple, peak-to-peak Pin Name UVDD = AVDD HVDDn UVDD AVDD BVDD FVDD VDD UVDD AVDD XTAL1 4 4 Min. 3.5 4.75 Typ. 5 5 Max. 5.5 5.25 200 Unit V V mV
dVDD/dt fXTAL fSYS fBUS Vil 1)
Supply voltage up/down ramping rate XTAL clock frequency CPU clock frequency, PLL on Program storage clock frequency, PLL on Automotive low input voltage
20 5
V/s MHz
For a list of available settings see Table 4-1.
U ports H ports P ports U ports, TEST, TEST2 H ports P ports U ports H ports P ports U ports,TEST, TEST2 H ports P ports RESETQ RESETQ 0.86 x xVDD 0.7 x xVDD
0.5 x xVDD 0.3 x xVDD
V
CMOS low input voltage
V
Vih 1)
Automotive high input voltage
V
CMOS high input voltage
V
RVil WRVil
Reset active input voltage Reset active input voltage during power-saving modes and wake reset Reset inactive and alarm active input voltage
0.75 0.4
V V
RVim
1)
RESETQ
1.5
2.3
V
For a list of input types and their supply voltages see Table 2-2 of document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1DS).
14
Feb. 10, 2005; 6251-589-1DS
Micronas
DATA SHEET
CDC 3207G-C3
Table 3-2: All voltages listed are referenced to ground (UVSS = HVSSn = AVSS = 0 V), except where noted. All ground pins except VSS must be connected to a low-resistive ground plane close to the IC. Symbol RVih WRVih Parameter Reset inactive and alarm inactive input voltage Reset inactive input voltage during power-saving modes and wake reset Ext. ADC reference input voltage ADC port input voltage referenced to ext. VREF reference ADC port input voltage referenced to int. VREFINT reference Pin Name RESETQ RESETQ Min. 3.2 UVDD - 0.4 V 2.56 0 0 AVDD VREFi VREFINT Typ. Max. Unit V V
VREFi PVi
VREF P ports
V V
3.3. Characteristics
Listed are only those characteristics that differ from Chapter 3.3 of Document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1DS). All not differing characteristics, that are not listed here, apply, but in a TCASE temperature range extended to -40 C to +105 C. Table 3-3: UVSS = FVSS = HVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD < 5.5 V, 4.75 V < HVDDn < 5.25 V, TCASE = -40 C to +105 C, fXTAL = 5 MHz, external components according to Fig. 2-3 (unless otherwise noted). Symbol Package Rthjc Rthja Thermal resistance from junction to case Thermal resistance from junction to ambient 9 31 K/W K/W measured on Micronas typical 2-layer board, 1s1p, described in document "Integrated Circuits - Thermal Characterization of Packages" (6200266-1E) (modified JESD-51.3) Parameter Pin Na. Min. Typ. 1) Max. Unit Test Conditions
Supply Currents (CMOS levels on all inputs, i.e., Vil = xVSS 0.3 V and Vih = xVDD 0.3 V, no loads on outputs) UIDDp UIDDprog UIDDf UIDDs UVDD PLL mode supply current UVDD Flash program supply current UVDD FAST mode supply current UVDD SLOW mode supply current UVDD UVDD UVDD UVDD see
Fig. 3-1
65 120 45 18 1.4
mA mA mA mA
fSYS = 24 MHz fSYS = 50 MHz Flash Write/Erase, all modules off, 2) all modules off, 2) all modules off, 2) 3)
1) Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested. 2) 3)
Value may be exceeded with unusual hardware option setting. Measured with external clock. Add typically 120 A for operation on quartz with SR0.XTAL=0 (Oscillator RUN mode).
Micronas
Feb. 10, 2005; 6251-589-1DS
15
CDC 3207G-C3
DATA SHEET
Table 3-3: UVSS = FVSS = HVSSn = AVSS = 0 V, 3.5 V < AVDD = UVDD < 5.5 V, 4.75 V < HVDDn < 5.25 V, TCASE = -40 C to +105 C, fXTAL = 5 MHz, external components according to Fig. 2-3 (unless otherwise noted). Symbol UIDDd UIDDw UIDDst Parameter UVDD DEEP SLOW mode supply current UVDD WAKE mode supply current UVDD STANDBY mode supply current Pin Na. UVDD UVDD UVDD UVDD UIDDi UVDD IDLE mode supply current UVDD 0 Min. Typ. 1) see
Fig. 3-1
Max. 0.9 50 75 100 475 500 0.6 2
Unit mA A A A A A mA mA A A
Test Conditions all modules off, 3) RC and XTAL oscillators off RC oscillator on, XTAL off XTAL oscillator on, RC off 3) RC oscillator on, XTAL off XTAL oscillator on, RC off 3) ADC on, PLL off ADC, buffer and PLL on ADC and PLL off no output activity, SM module off
20 35 60 50 see
Fig. 3-1
AIDDa
AVDD active supply current
AVDD
0.35
AIDDq HIDDq
Quiescent supply current
AVDD Sum of all HVDDn
0 0
1 1
10 40
Inputs Ii
1)
Input leakage current
TEST2
-1
1
A
0 < Vi < UVDD
Typical values describe typical behavior at room temperature (25 C, unless otherwise noted), with typical Recommended Operating Conditions applied, and are not 100% tested.
2) 3)
Value may be exceeded with unusual hardware option setting. Measured with external clock. Add typically 120 A for operation on quartz with SR0.XTAL=0 (Oscillator RUN mode).
16
Feb. 10, 2005; 6251-589-1DS
Micronas
DATA SHEET
CDC 3207G-C3
A 900 800 700 UIDDs (SLOW mode) 600 UIDD 500 400 UIDDd (DEEP SLOW mode) 300 200 100 0 -40 -30 -20 -10 UIDDi (IDLE mode)
0
10
20
30
40
50 TCASE
60
70
80
90
100 110 120 C
Fig. 3-1: Typical UIDD characteristics over temperature @ fXTAL = 4 MHz, 5 V
3.4. Recommended Quartz Crystal Characteristics
See Chapter 3.4 of document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1DS).
Micronas
Feb. 10, 2005; 6251-589-1DS
17
CDC 3207G-C3
DATA SHEET
18
Feb. 10, 2005; 6251-589-1DS
Micronas
DATA SHEET
CDC 3207G-C3
4. CPU and Clock System
4.1. Recommended Register Settings
Settings for PMF, IOP and WSR differing from those given in Table 4-1 must not be used and may result in undefined behavior. It is required not to operate I/O faster than Flash. Suppression Strength (SUP) and Clock Tolerance (TOL) may be varied between zero and the values for strong settings according to the rules in Section 4.4.2 of the document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251-579-1DS). The given limits must not be exceeded.
Table 4-1: PLL and ERM modes: Recommended settings and resulting operating frequencies (MHz) fXTAL CPU Flash I/O ERMC.EOM = 1 Weak SUP TOL fSYS 4 16 24 PLLC. PMF 3 5 fBUS 8 8 12 32 7 8 10.67 WSR fIO= f0 8 8 IOC. IOP 1 2 Normal SUP TOL Strong SUP TOL ERMC.EOM = 2 or 3 Weak SUP TOL Normal SUP TOL Strong SUP 22 31 33 31 19 23 37 37 42 14 28 28 30 35 37 TOL 11 12 2 12 9 7 6 6 1 7 8 10 9 8 6
0x11 0x22 0x11 0x33 0x22
0 0 0
8 12 10 12 12
0 0 0 0 0
14 15 10 12 12
0 0 0 0 0
15 15 10 12 12
8 12 12 16 16
4 6 2 8 8
14 21 21 28 19 23 28 35 42 8 17 24 26 35
7 11 2 12 9 7 6 6 1 4 8 12 11 6
8
3
0 0
40 48 5 10 20 30
9 11 1 3 5
10 12 10 10 10
0x33 0x33 0x00 0x11 0x22
8 8 10 10 10
4 5 0 1 2
0 0 0 0 0
6 1 5 10 14
0 0 0 0 0
6 1 8 15 14
0 0 0 0 0
6 1 14 15 14
21 25 5 10 15
6 1 3 5 8
40 50
7 9
10 12.5
0x33 0x33
10 10
3 4
0
6
0
6
0
6
21
6
set ERMC.EOM=0
set ERMC.EOM=0
Micronas
Feb. 10, 2005; 6251-589-1DS
19
CDC 3207G-C3
DATA SHEET
20
Feb. 10, 2005; 6251-589-1DS
Micronas
DATA SHEET
CDC 3207G-C3
5. Memory and Special Function ROM (SFR) System
address range
(16M) 00FF.FFFF CR.MAP = 00
RESETQ = 1
CR.MAP = 01 CR.MAP = 1x
RESETQ = 0
TEST2-Pin = 0 TEST2-Pin = 1
.5M
F8.0000
I/O
I/O
I/O
F0.0000
.5M rsvd debug
SFR
SFR
SFR
E0.0000
2M
C0.8000
RAM 32KB
C0.0000
RAM 32KB
RAM 32KB
A0.0000
8M
The device contains a 512-KByte Flash EEPROM of the AMD Am29LV400BT type (top boot configuration). This device exhibits electrical byte program and sector erase functions. Refer to the AMD data sheet for details.
28.0000
Flash 512KB
20.0000
Flash 512KB
8.0000 8000
2M RAM 32KB Flash 512KB SFR Flash 512KB SFR
0
Fig. 5-1: Address map. Most common settings
Micronas
Feb. 10, 2005; 6251-589-1DS
21
CDC 3207G-C3
Warning: Since only a 24-bit address space is supported, do not use addresses outside this range when debugging this device.
DATA SHEET
22
Feb. 10, 2005; 6251-589-1DS
Micronas
DATA SHEET
CDC 3207G-C3
6. Core Logic
6.1. Control Word (CW)
A number of important system configuration properties are selectable during device start-up by means of a unique control word (CW). As Table 6-1 shows, the device disables external access (through the multifunction port) to internal code, as long as MFPLR.MFPL is 1 (= state after UVDD power-up). Setting it to 0 requires internal SW. By this means, an effective device lock mechanism is implemented, which prevents unauthorized access to internal SW. In ROM parts, flag MFPLR.MFPL is available, but does not lock the multifunction port. Thus Table 6-1 reduces to Table 6-2.
6.1.1. Reset Active
At the end of the reset period, the device fetches this CW from address locations 0x20 to 0x23 of a source that is determined by the state of pins TEST and TEST2 and flag MFPLR.MFPL, see Table 6-1 for MCM parts, Table 6-2 for ROM parts.
Table 6-2: CW fetch in ROM parts (QFP128)
"Control Word Fetch" desired from Necessary Reset config. of pins TEST2 Internal ROM External via multifunction port Int. special-function ROM 0 0 1 TEST 0 1 x
Table 6-1: CW fetch in MCM parts (QFP128)
"Control Word Fetch" desired from Necessary Reset Configuration TEST2 Int. Flash Int. Flash Ext. via multifunction port Int. special-function ROM
1)
TEST 0 1
MFPL x 1 0 1)
0 0
1
x
x
6.1.2. Reset Inactive
When exiting Reset, the CW is read and stored in the control register (CR) and the system will start up according to the configuration defined therein. Normally the CW is fetched from the same memory that the system will start executing code from. Table 6-3 gives fixed CWs for a list of the most commonly used configurations.
Only available after a non-power-on RESET with MFPL = 0 set before
Table 6-3: Some common system configurations and the corresponding CW setting
Part Type MCM ROM "Program Start" desired from Additional desired properties Necessary CW 31:16 int. 16-bit Flash int. 16-bit ROM Don't care Don't care 15:0 0x7F5F 0x7F5F
Micronas
Feb. 10, 2005; 6251-589-1DS
23
CDC 3207G-C3
DATA SHEET
24
Feb. 10, 2005; 6251-589-1DS
Micronas
DATA SHEET
CDC 3207G-C3
7. Hardware Options
7.1. Functional Description
Hardware options are available in several areas to adapt the IC function to the host system requirements. For details see the document "CDC32xxG-C Automotive Controller - Family User Manual, CDC3205G-C Automotive Controller" (6251579-1DS). Setting hardware options is carried out in two steps: 1. selection is effected by programming dedicated address locations in the HW options field with the desired options' code. 2. activation is effected by copying the HW options field to the corresponding HW options' registers at least once after each reset. In EMU and MCM devices, all hardware options are software-progammable. In mask ROM derivatives, the clock options and the watchdog, clock and supply monitors are hard-wired, according to the HW options field of the ROM code hex file. Those options can only be altered by changing a production mask. To ensure compatible option settings in this IC and mask ROM derivatives when run with the same ROM code, it is mandatory to always write the HW options field to the HW option registers directly after reset.
Micronas
Feb. 10, 2005; 6251-589-1DS
25
CDC 3207G-C3
DATA SHEET
26
Feb. 10, 2005; 6251-589-1DS
Micronas
DATA SHEET
CDC 3207G-C3
8. Differences
This chapter describes differences between this document and predecessor document: "CDC3207G-C Automotive Controller Specification" (6251-589-1PD).
Section 1. Introduction 2. Pins 3. Electrical Characteristics Description Table 1-1: devices added Figure 2-3 changed. Characteristics: Values changed: Rthjc, Rthja, UIDDp, UIDDf, UIDDi, AIDDa 4. CPU and Clock System 5. Memory and Special Function ROM System Table 4-1: entry for fXTAL = 4 MHz, fSYS = 8 MHz deleted Table 4-2: deleted Figure 5-1: Flash upper hex address corrected Precaution added
Micronas
Feb. 10, 2005; 6251-589-1DS
27
CDC 3207G-C3
9. Data Sheet History 1. Advance Information: "CDC3207G-C V1.0 Automotive Controller Specification", Feb. 21, 2002, 6251-589-1AI. First release of the advance information. Originally created for HW version CDC3207G-C1. 2. Advance Information: "CDC3207G-C V2.0 Automotive Controller Specification", June 6, 2002, 6251-589-2AI. Second release of the advance information. Originally created for HW version CDC3207G-C2. 3. Advance Information: "CDC3207G-C Automotive Controller Specification", April 15, 2003, 6251-589-3AI. Third release of the advance information. Originally created for HW version CDC3207G-C3. 4. Preliminary Data Sheet: "CDC3207G-C Automotive Controller Specification", June 12, 2003, 6251-589-1PD. First release of the preliminary data sheet. Originally created for HW version CDC3207G-C3. 5. Data Sheet: "CDC3207G-C3 Automotive Controller Specification", Feb. 10, 2005, 6251-589-1DS. First release of the data sheet. Originally created for HW version CDC3207G-C3.
DATA SHEET
Micronas GmbH Hans-Bunte-Strasse 19 D-79108 Freiburg (Germany) P.O. Box 840 D-79008 Freiburg (Germany) Tel. +49-761-517-0 Fax +49-761-517-2174 E-mail: docservice@micronas.com Internet: www.micronas.com Printed in Germany Order No. 6251-589-1DS
All information and data contained in this data sheet are without any commitment, are not to be considered as an offer for conclusion of a contract, nor shall they be construed as to create any liability. Any new issue of this data sheet invalidates previous issues. Product availability and delivery are exclusively subject to our respective order confirmation form; the same applies to orders based on development samples delivered. By this publication, Micronas GmbH does not assume responsibility for patent infringements or other rights of third parties which may result from its use. Further, Micronas GmbH reserves the right to revise this publication and to make changes to its content, at any time, without obligation to notify any person or entity of such revisions or changes. No part of this publication may be reproduced, photocopied, stored on a retrieval system, or transmitted without the express written consent of Micronas GmbH.
26
Feb. 10, 2005; 6251-589-1DS
Micronas

▲Up To Search▲

Price & Availability of CDC3207G-C

	To Download CDC3207G-C Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .